Monolithic Power Integrated Circuits (PICs) for high-voltage applications may sometimes integrate thereon analog and digital circuitry. For example, one type of power integrated circuits is a DC-to-DC converter which may integrate the controller and one or both of the power switches on a single integrated circuit. As thus integrated, CMOS devices forming the analog circuits in the power integrated circuit need to be isolated from the noisy substrate to avoid circuit malfunction due to noise. In particular, the analog circuits typically include sensitive circuitry such as bandgap, amplifier and sensing circuits. The digital circuits typically include the oscillator, logic circuitry and the PWM controller. Conventional power integrated circuit includes separate ground connection for the analog circuits (analog ground) and for the digital circuits (digital ground). The substrate of the power integrated circuit, typically a P-type substrate, is typically connected to the digital ground which tends to be noisy due to the switching action of the digital clocking circuitry. The sensitive CMOS analog circuits of the power integrated circuit need to be isolated from the P-type substrate and the noisy digital ground.
In the CMOS analog circuits, PMOS devices are self-isolated from the P-type substrate by the virtue of being formed in N-wells. However, NMOS devices are formed in P-wells and are thus directly connected to the P-type substrate if not isolated. Conventional power integrated circuits isolate the CMOS devices from the P-substrate by using an N-type buried layer (“N-buried layer”) and deep N-well ring connected to the N-type buried layer. FIGS. 1 and 2 illustrate the conventional CMOS device isolation structure in an integrated circuit. Referring to FIGS. 1 and 2, an integrated circuit 1 is typically formed using one or more circuit blocks 1-3, each circuit block housing analog or digital circuits. In the example shown, each of the circuit blocks 1-3 is isolated by a CMOS device isolation structure including a deep N-well ring 5 and an N-type buried layer 14 underlying the entire area within the circuit block defined by the ring 5. As shown in the example circuit block 10 of FIG. 2, the N-buried layer 14 extends across the entire area under the circuit block between the deep N-well ring 5. PMOS and NMOS devices are then formed in respective N-well 18 and P-well 20 in the epitaxial layer 13 above the N-buried layer 14. As thus configured, the PMOS and NMOS devices are completely enclosed by the deep N-well ring 5 and the N-buried layer 14 and are thus isolated from the P-type substrate 12 which is typically connected to the digital ground. Although it is more critical to isolate the analog circuit blocks from the noisy P-type substrate, conventional integrated circuits typically isolate both the analog and the digital circuit blocks to keep the substrate less noisy which results in lower noise coupling from substrate to analog blocks.
Although the conventional CMOS device isolation structure is effective, the isolation structure takes up large amount of silicon area because of the use of the deep N-well ring. Deep N-well is typically associated with large out-diffusion. Therefore, it is necessary to have a large spacing between adjacent deep N-wells. Thus, the die size for the integrated circuit formed using the conventional CMOS device isolation structure tends to be large, increasing the cost of the integrated circuit.